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ZR36011 september 1993 zoran corporation n 1705 wyatt drive n santa clara, ca 95054 n (408) 986-1314 n fax (408) 986-1240 digital color space converter preliminary n rgb to ycbcr and ycbcr to rgb conversions n cymaye to ycbcr and ycbcr to cymaye conversions n bidirectional data buses for convenient interfacing n pixel rates up to 30 megapixels per second n supports 4:2:2 decimation and interpolation modes, with optional ?ltering n supports 4:1:1 decimation and interpolation with ?ltering features n ccir601 and full range data scaling options n bidirectional shift registers for sync pulse delay matching n compatible with zorans zr36050 jpeg image compression processor and zr36015 raster to block converter n 100-pin pqfp package n low power cmos, 5v n image processing applications general description the ZR36011 digital color space convertor performs forward or inverse conversions between rgb and ycbcr color spaces. it is intended for use as a building block in systems that require this function. the direction of the conversion (rgb to ycbcr or ycbcr to rgb), and all other operating mode options, are deter- mined by the states of control inputs. the 24-bit rgb and ycbcr data buses are bidirectional, making for straightforward interfac- ing when the direction of signal flow is reversible, as in a video compression and expansion module. conversion between cymaye (cyan, magenta, yellow) and ycbcr color spaces is also supported. an additional conversion stage, between rgb and cymaye color spaces, is inserted in this case, thus redefin- ing the r, g, b pins as cy, ma, ye. the color space conversion coefficients are fixed. one of two sets of coefficients can be selected: one suitable for component figure 1. ZR36011 block diagram 2 8 8 bidirectional i/o sign ccir bypass srgb 8 r g b delay line color space conversion rounding, limiting decimation interpolation filtering syc bidirectional i/o 8 8 8 y cb cr cmy mode clk rst chs oe dir control 3 2 signal ranges conforming to ccir recommendation 601, the other for components occupying the full 8 bit numeric range. decimation and interpolation of the color difference signals is supported. the available modes are 4:4:4 (undecimated), 4:2:2 and 4:1:1. filtering is optional in the 4:2:2 mode, and is always performed in the 4:1:1 mode. other operating modes allow simple two-to-one compression to be performed by an additional decimation of the y, cb and cr data, as well as the correspond- ing decompression by interpolation. a two-bit bidirectional shift register, with the same number of stages (eight) as the computation pipeline, is provided. this can be used as a delay line for synchronization signals, to keep them synchronized with the data. n image capture and display n image compression this document was created with framemaker 4.0.4
ZR36011 preliminary 2 table 1. signal description name type description v cc power +5 volt power. all v cc pins must be connected to +5 volts. v ss power power supply ground. all v ss pins must be connected to ground. clk input system clock input. input data and sync signals are latched on the rising edge of clk, and output data and sync signals change state following the rising edge of clk. rst input reset, active low. must be kept low for at least two clock cycles to reset the device. when active, all stages of the sync delay lines are initialized to the high state, and the delay line output (srgb if dir is high, or syc if dir is low) is high. r(7-0) i/o red component data if cmy is low, or cyan if cmy is high. 8 bits unsigned. r is an input if dir is low, and an output if dir is high. g(7-0) i/o green component data if cmy is low, or magenta if cmy is high. 8 bits unsigned. g is an input if dir is low, and an output if dir is high. b(7-0) i/o blue component data if cmy is low, or yellow if cmy is high. 8 bits unsigned. b is an input if dir is low, and an output if dir is high. srgb(1-0) syc(1-0) i/o sync delay line inputs and outputs. if dir is low, srgb is the input and syc is the output, and vice versa if dir is high. input level changes appear at the output with a delay of 8 clock cycles. since the delay line output is ini- tialized to high by rst , these signals are considered active low. y(7-0) i/o luminance component data. 8 bits unsigned. y is an output if dir is low, and input if dir is high. cb(7-0) i/o blue color difference (cb) component data. 8 bits unsigned if sign is low, or 8 bits twos complement if sign is high. cb is an output if dir is low, and input if dir is high. in 4:2:2 and 4:1:1 modes, cb is unused (if outputs, all cb pins are high). cr(7-0) i/o red color difference (cr) component data. 8 bits unsigned if sign is low, or 8 bits twos complement if sign is high. cr is an output if dir is low, and input if dir is high. in 4:2:2 and 4:1:1 modes, cb and cr data are multi- plexed on cr. dir input direction control. if dir is low, rgb (or cymaye) to ycbcr conversion is performed. if dir is high, ycbcr to rgb (or cymaye) conversion is performed. cmy input cymaye color space control. if cmy is low, conversion between rgb and ycbcr color spaces is performed. if cmy is high, the r, g and b inputs or outputs are complemented, with the result that conversion between cymaye and ycbcr color spaces is performed. ccir input signal level control. if ccir is low, input and output data may occupy the full 8 bit signal level range. if ccir is high, input and output data signal levels conform to ccir recommendation 601-2. chs input chrominance multiplex synchronization signal. the rising edge of this signal is used to synchronize an internal toggle that controls the multiplexing of the cb and cr component data on the cb pins, in the operating modes with decimated chrominance. in operating modes with decimated luminance, it determines the temporal alignment of the decimated data. sign input chrominance numerical representation control. the cb and cr data is unsigned if sign is low, and twos comple- ment if sign is high. oe input output enable. when low, all outputs are enabled. when high, all outputs are disabled (floating). oe also disables the internal clock of the device when it is high, thus freezing all internal processing.
ZR36011 3 preliminary mode(2-0) input component decimation mode control. the decimation and interpolation modes are selected using mode as shown follows: bypass input conversion bypass control. if bypass is high, the color space conversion computation is bypassed, but all deci- mation mode selections and control inputs are still operational. the data pipeline delay of 8 clock cycles is not affected by the activation of bypass. table 1. signal description (continued) name type description decimation mode selection (0=low, 1=high) mode2 mode1 mode0 description 0 0 0 4:4:4, no decimation or interpolation 0 0 1 4:2:2 chrominance decimation or interpolation without filtering 0 1 0 4:2:2 chrominance decimation or interpolation with filtering 0 1 1 4:1:1 chrominance decimation or interpolation 1 0 0 not used 1 0 1 not used 1 1 0 4:4:4, with 2 to 1 decimation or interpolation of all three ycbcr components 1 1 1 4:2:2, with 2 to 1 additional decimation or interpolation of all three ycbcr components
ZR36011 preliminary 4 functional overview color space conversion rgb <-> ycbcr the color space conversion block (see figure 1) performs con- version between rgb and ycbcr color spaces, with built in conversion coefficients. one of two data scaling and limiting modes can be selected by means of the ccir control input, one (with ccir low) intended for data occupying the full 8 bit signal level range, the other (with ccir high) intended for data occu- pying the range of values specified by ccir recommendation 601-2. the conversions are performed as follows: forward direction, dir = low: with ccir low (8 bit full range data): y = 0.299r + 0.587g + 0.114b cr = 0.713(r-y) cb = 0.564(b-y) with ccir high (data conforming to ccir): y = 0.299r + 0.587g + 0.114b cr = 0.729(r-y) cb = 0.577(b-y) inverse direction, dir = high: with ccir low (8 bit full range data): r = y + 1.402cr g = y - 0.714cr - 0.344cb b = y + 1.772cb with ccir high (data conforming to ccir): r = y + 1.37cr g = y - 0.698cr - 0.336cb b = y + 1.73cb internally, the color space conversion coefficients are represent- ed with a precision of 12 bits. rgb <-> cymaye when the cmy control input is high, the 8 bit r, g and b data are logically complemented in the i/o block, thus performing an additional conversion between the internal r, g, b and external cy, ma, ye. this is equivalent to the following conversion formula: cy = 255 - r ma = 255 - g ye = 255 - b numerical representation the results of the color space conversion are rounded to produce 8 bit results, and limited to prevent wrap-around. when ccir is high, r, g, b, and y occupy 220 levels, and cr and cb occupy 225 levels. input data outside the allowed range of levels is internally limited, and output data is limited to the allowed range. when ccir is low, inputs can occupy the full 8 bit range, and outputs are limited to this range. cr and cb can have either twos complement or offset binary representations, as selected by the sign control input. r, g, b and y always have unsigned magnitude representation. tables 2 and 3 show, for ccir low and ccir high, respectively, the equivalent decimal number represented by each hexadeci- mal value of the data inputs and outputs. table 2. numerical representation, ccir = low hexadecimal value decimal equivalent r, g, b, y (unsigned) cr, cb offset binary (sign = low) twos compliment (sign = high) ff 255 127 -1 fe 254 126 -2 ... ... ... ... 81 129 1 -127 80 128 0 -128 7f 127 -1 127 ... ... ... ... 01 1 -127 1 00 0 -128 0 table 3. numerical representation, ccir = high hexadecimal value decimal equivalent r, g, b, y (unsigned) cr, cb offset binary (sign = low) twos compliment (sign = high ff 235 112 -1 fe 235 112 -2 ... ... .... ... f1 235 112 -15 f0 235 112 -16
ZR36011 5 preliminary conversion bypass when the bypass control input is high, the color space conver- sion block (figure 1), and consequently the rgb <-> ycbcr color space conversion computation, is bypassed. all the other functional blocks, and all control inputs, continue to operate nor- mally. thus, when bypass is high, the device can be utilized as a data format convertor, for example: n with cmy high, and mode(2-0) = 000, as a rgb to cymaye convertor ef 235 111 -17 ee 235 110 -18 ed 235 109 -19 ec 235 108 -20 eb 235 107 -21 ea 234 106 -22 ... ... ... ... 91 145 17 -111 90 144 16 -112 8f 143 15 -112 ... ... ... ... 81 129 1 -112 80 128 0 -112 7f 127 -1 112 ... ... ... ... 71 113 -15 112 70 112 -16 112 69 111 -17 111 ... ... ... ... 11 17 -111 17 10 16 -112 16 0f 16 -112 15 ... ... ... 01 16 -112 1 00 16 -112 0 table 3. numerical representation, ccir = high (continued) hexadecimal value decimal equivalent r, g, b, y (unsigned) cr, cb offset binary (sign = low) twos compliment (sign = high n with mode(2-0) = 010, to perform conversions between 4:4:4 and 4:2:2 formats n with mode(2-0) = 110, to perform 2:1 decimation and interpolation of all three components input to output latency the output data has a latency or pipeline delay of eight clock cycles. this latency is constant, in all modes of operation, regardless of the direction of conversion, decimation or interpo- lation setting, or whether the color space conversion is bypassed or not. delay line the delay line consists of an eight stage shift register with a two bit wide data path. its delay is equal to the latency of the data outputs. thus, it is useful as a matching delay line for horizontal and vertical video synchronization signals, to keep them in syn- chronization with the data flowing through the device. the rst input resets all stages of the delay line to the high state, and consequently the output (syc or srgb depending on the state of dir) is also high when reset is active. the delay line is therefore suitable for active low synchronization signals. the input at syc or srgb is effectively ignored when rst is active, and is clocked into the delay line starting from the second rising edge of clk following the deactivation of rst , as shown in figure 2. output enable and pipeline freeze the oe input simultaneously controls the enabling of all output pins (color components and delay line), and the freezing of the computational pipeline. when oe is low, the output pins are enabled, and data is clocked through the pipeline. when oe goes high, the outputs go into a high impedance state, and the clock is disabled internally starting at the second rising edge of clk following the rising edge of oe , thus freezing all operations in their current state, including the color space conversion com- putation, decimation and interpolation, and the delay line. input data is ignored while the clock is disabled. the clock is enabled clk rst delay line input data (0) data (7) data (8) data (9) delay line output data (0) data (1) 8 clock cycles figure 2. delay line reset timing
ZR36011 preliminary 6 again starting at the second rising edge of clk following the falling edge of oe . note that since oe enables and disables the internal clock, it is a synchronous input and must have sufficient setup and hold time. see figure 3 for an example of the opera- tion of oe . decimation and interpolation modes the three mode control pins select the operating mode of the decimation and interpolation function block, as shown in table 1. decimation is performed in forward color space conver- sion (dir = low), and interpolation is performed in inverse color space conversion (dir = high). whenever decimation or interpolation of the luminance and/or chrominance data is performed (all modes with the exception of mode = 000), each data sample on the y, cb, cr pins occupies more than one clock cycle, or the chrominance data is multiplexed on the cr pins, or both (multiplexed chrominance samples that occupy more than one clock cycle each). the chs input signal must be used, as shown in the timing diagrams for each of the modes, to synchronize the operation of the device to the data on the y, cr, cb pins. the second rising edge of clk following the rising edge of chs always samples the first input data point. chs is used to initialize the state of the internal mechanism that subsequently maintains the synchronization. mode = 000 in this mode no decimation or interpolation is performed. ycbcr pixels are 24 bits wide; the cr pins carry the cr data and the cb pins carry the cb data. a timing diagram for forward conversion is shown in figure 3; inverse conversion in this mode has iden- tical timing, except that the functions of the r, g, b pins are exchanged with those of the y, cr, cb pins. the operation of the oe signal is also depicted in figure 3. chs is not used in this mode of operation. mode = 001 in this mode, ycbcr data is in 4:2:2 format. the cb pins are not used; cb and cr data are multiplexed on the cr pins. the cb and cr samples are co-sited with the y sample that is simulta- clk oe r, g, b (input) r, g, b (n) y, cr, cb (output) figure 3. rgb to ycbcr conversion, mode = 000, also showing oe timing r, g, b (n+1) r, g, b (n+2) r, g, b (n+3) r, g, b (n+4) r, g, b (n+10) r, g, b (n+11) r, g, b (n+12) r, g, b (n+13) r, g, b (n+14) y, cr, cb (n-8) y, cr, cb (n-7) y, cr, cb (n-6) y, cr, cb (n) y, cr, cb (n+1) y, cr, cb (n+4) y, cr, cb (n+5) y, cr, cb (n+6) neous with the cb sample. cb and cr are decimated in forward conversion by dropping the unused samples, and interpolated in inverse conversion by replication. no filtering is performed in either direction. figures 4 and 5, respectively, illustrate how the decimation and interpolation are performed. chs determines the validity of input data and synchronizes the multiplexing of cr and cb on the cr pins. as shown in figure 6 for forward conversion, and figure 7 for inverse conversion, the second rising edge of clk following the rising edge of chs latches the first valid input data sample and determines the mul- tiplex order. data output: y cr y (n) y (n+1) y (n+2) y (n+3) cb (n) cr (n) cb (n+2) cr (n+2) y y0 cr0 cb0 cb0 cr y1 cr1 cb1 cr0 y2 cr2 cb2 cb2 y3 cr3 cb3 cr2 y4 cr4 cb4 cb4 y5 cr5 cb5 cr4 figure 4. illustration of decimation method, mode = 001 data input: y cr y (n) y (n+1) y (n+2) y (n+3) cb (n) cr (n) cb (n+2) cr (n+2) y y0 cb0 cb0 cr y1 cr0 y2 cr2 cb2 y3 cb4 y4 y5 cr4 figure 5. illustration of interpolation method, mode = 001 y (n+4) cb (n+4) cr0 cr0 cr2 cr2 cr4 cr4 cb0 cb2 cb2 cb4 cb4 interpolator output: y (n) cr (n) cb (n) y (n+1) cr (n) cb (n) y (n+2) y (n+3) cr (n+2) cb (n+2) cr (n+2) cb (n+2)
ZR36011 7 preliminary mode = 010 this mode is similar to mode = 001, with the addition of a filter- ing stage in decimation and interpolation. a three tap decimation filter is used, and the interpolation is performed by averaging adjacent samples. this is illustrated in figures 8 and 9, respectively. clk r, g, b (input) y, cr (output) figure 6. rgb to ycbcr timing, mode = 001 rgb (0) rgb (1) rgb (8) rgb (9) rgb (10) rgb (11) y(0) cb(0) y(1) cr(0) y(2) cb(2) y(3) cr(2) chs clk r, g, b (output) y, cr (input) figure 7. ycbcr to rgb timing, mode = 001 rgb (0) rgb (1) y(7) cr(6) y(8) cr(8) y(9) cr(8) y(10) cr(10) y(0) cb(0) y(1) cr(0) chs y(11) cr(10) rgb (2) rgb (3) data output: y cr y (n) y (n+1) cb(n-1)+2cb(n)+cb(n+1) y y0 cr0 cb0 cb0 cr y1 cr1 cb1 cr0 y2 cr2 cb2 cb2 y3 cr3 cb3 cr2 y4 cr4 cb4 cb4 y5 cr5 cb5 cr4 figure 8. illustration of decimation method, mode = 010 4 cr(n-1)+2cr(n)+cr(n+1) 4 cb(n+1)+2cb(n+2)+cb(n+3) 4 cr(n+1)+2cr(n+2)+cr(n+3) 4 y (n+2) y (n+3) cr-1 cb-1 the signal timing in mode = 010 is as shown in figures 6 and 7. data input: y cr y (n) y (n+1) y y0 cb0 cb0 cr y1 cr0 y2 cb2 cr2 y3 cr2 y4 cb4 cr4 y5 cr4 figure 9. illustration of interpolation method, mode = 001 cr(n)+cr(n+2) 2 y (n+2) y (n+3) interpolator output: y (n) cr (n) cb (n) cb (n) y (n+1) cr(n+2)+cr(n+4) 2 cb(n)+cb(n+2) 2 cr (n) cb (n+2) cr (n+2) y (n+2) cb (n+2) cb(n+2)+cb(n+4) 2 cr (n+2) y (n+3) cr0 cr0+cr2 2 cb0+cb2 2 cb2 cb4 cr2+cr4 2 cr4+cr6 2 cb2+cb4 2 cb4+cb6 2
ZR36011 preliminary 8 mode = 011 in this mode, ycbcr data is in 4:1:1 format, with one sample each of cb and cr for every four samples of y. cb and cr are multiplexed on the cr pins, valid for two clock cycles each.the cb pins are not used. decimation in forward conversion, and interpolation in inverse conversion, are performed as illustrated in figures 10 and 11. data output: y cr y y0 cr0 cb cr y1 cr1 y2 cr2 y3 cr3 y4 cr4 y5 cr5 figure 10. illustration of decimation method, mode = 011 cb(n-1)+2cb(n)+cb(n+1) cr(n+1)+2cr(n+2)+cr(n+3) cb(n+3)+2cb(n+4)+cb(n+5) 444 y (n) y (n+1) y (n+2) y (n+3) y (n+4) y (n+5) cb0 cb1 cb2 cb3 cb4 cb5 cr cb chs determines the validity of input data and synchronizes the multiplexing of cr and cb on the cr pins. as shown in figure 12 for forward conversion, and figure 13 for inverse conversion, the second rising edge of clk following the rising edge of chs latches the first valid input data sample and determines the mul- tiplex order. data input: y y y0 cr y1 y2 cr2 y3 y4 y5 figure 11. illustration of interpolation method, mode = 011 cr(n-2)+cr(n+2) 2 y (n) y (n+1) y (n+2) y (n+3) y (n+4) y (n+5) cb0 cb4 cb (n) cr (n+2) cb (n+4) interpolator output: cb (n) cr (n+2) cb(n)+cb(n+4) 2 y (n) y (n+1) y (n+2) y (n+3) y (n+4) y (n+5) cb (n+4) cr(n+2)+cr(n+6) 2 y6 y7 cr cr2 cb0+cb4 2 cr2+cr6 2 cb4 cr6 cb4+cb8 2 cr6 clk r, g, b (input) y (output) figure 12. rgb to ycbcr timing, mode = 011 rgb (0) rgb (1) rgb (8) rgb (9) rgb (10) rgb (11) y(0) y(1) y(2) y(3) chs cr (output) rgb (12) rgb (13) y(4) y(5) cb(0) cr(2) cb(4)
ZR36011 9 preliminary mode = 110 in this mode, the ycbcr format is 4:4:4, but the ycbcr pixel rate is one half the rgb pixel rate. the cr pins carry the cr data and the cb pins carry the cb data. in forward conversion, the ycbcr data is 2:1 decimated through a three tap filter, as illustrated in figure 14. in inverse conversion, the input ycbcr data is inter- polated by averaging two adjacent samples, as illustrated in figure 15. clk r, g, b (output) y (input) figure 13. ycbcr to rgb timing, mode = 011 rgb (0) rgb (1) y(0) y(1) chs rgb (2) rgb (3) y(2) y(3) y(8) y(9) y(10) y(11) y(12) cr (input) cb(0) cr(2) cb(8) cr(10) rgb (4) data output: y cr y y0 cr0 cr y1 cr1 y2 cr2 y3 cr3 y4 cr4 y5 cr5 figure 14. illustration of decimation, mode = 110 y(n-1)+2y(n)+y(n+1) y(n+1)+2y(n+2)+y(n+3) y(n+3)+2y(n+4)+y(n+5) 444 cb0 cb1 cb2 cb3 cb4 cb5 cr(n-1)+2cr(n)+cr(n+1) cr(n+1)+2cr(n+2)+cr(n+3) cr(n+3)+2cr(n+4)+cr(n+5) 444 cb cb(n-1)+2cb(n)+cb(n+1) cb(n+1)+2cb(n+2)+cb(n+3) cb(n+3)+2cb(n+4)+cb(n+5) 444 cb y-1 y cr cb y cr cb y cr cb chs determines the validity of input data and synchronizes the half-clock-rate data transitions on the y, cr and cb pins. as shown in figure 16 for forward conversion, and figure 17 for inverse conversion, the second rising edge of clk following the rising edge of chs latches the first valid input data sample. data input: y y y0 cr y1 y2 figure 15. illustration of interpolation, mode = 110 y (n) y (n) interpolator output: y3 cr y(n)+y(n+1) 2 cb cr (n) cb (n) cr (n) cr (n) y (n+1) cr (n+1) cb (n+1) y (n+2) cr (n+2) cb (n+2) y (n+2) cr (n+2) cb (n+2) y(n) cr(n) cb(n) y(n+1)+y(n+2) 2 y(n+1) y(n+2) y(n+2)+y(n+3) 2 cr(n)+cr(n+1) 2 cr(n+1)+cr(n+2) 2 cr(n+1) cr(n+2) cr(n+2)+cr(n+3) 2 cb(n)+cb(n+1) 2 cb(n+1)+cb(n+2) 2 cb(n+1) cb(n+2) cb(n+2)+cb(n+3) 2 cb cr0 cb0 y0 cr0 cb0 y0+y1 2 cr0+cr1 2 cb0+cb1 2 cr1 cb1 y1 cr1 cb1 y1+y2 2 cr1+cr2 2 cb1+cb2 2 cr2 cb2 y2 cr2 cb2 y2+y3 2 cr2+cr3 2 cb2+cb3 2 cr3 cb3 y3 cr3 cb3 y (n+1) cr (n+1) cb (n+1)
ZR36011 preliminary 10 mode = 111 in this mode, ycbcr data is in 4:2:2 format, with cb and cr multiplexed on the cr pins, and the data rate of y, cb and cr is re duced by an additional factor of two. the decimation method for forward conversion is illustrated in figure 17, and the interpolation method for inverse conversion in figure 18. clk y, cr, cb (output) r, g, b (input) figure 16. rgb to ycbcr timing, mode = 110 rgb (0) y, cr, cb (0) chs rgb (1) rgb (8) rgb (9) rgb (10) rgb (11) y, cr, cb (2) clk r, g, b (output) y, cr, cb (input) figure 17. ycbcr to rgb timing, mode = 110 rgb (0) y, cr, cb (0) chs rgb (1) rgb (2) rgb (3) y, cr, cb (2) y, cr, cb (8) y, cr, cb (10) data output: y cr y y0 cr0 y y1 cr1 y2 cr2 y3 cr3 y4 cr4 y5 cr5 figure 18. illustration of decimation, mode = 111 y(n-1)+2y(n)+y(n+1) y(n+1)+2y(n+2)+y(n+3) y(n+3)+2y(n+4)+y(n+5) 444 cb0 cb1 cb2 cb3 cb4 cb5 cb(n-1)+2cb(n)+cb(n+1) cr(n+1)+2cr(n+2)+cr(n+3) cb(n+3)+2cb(n+4)+cb(n+5) 444 cr y-1 y cb y cr y cb y(n+5)+2y(n+6)+y(n+7) 4 cr(n+5)+2cr(n+6)+cr(n+7) 4
ZR36011 11 preliminary chs determines the validity of input data and synchronizes the half-clock-rate data transitions on the y, cr pins, and the mult iplexing of cb and cr. as shown in figure 20 for forward conversion, and figure 21 for inverse conversion, the second rising edge of clk following the rising edge of chs latches the first valid input data sample. data input: y y y0 cr y1 y2 figure 19. illustration of interpolation, mode = 111 y (n) y (n) interpolator output: y3 cr cb (n) cb (n) y (n+1) cr (n+1) y (n+1) cr (n+1) y (n+2) cb (n+2) y(n) cb(n) cr(n+1)+cr(n-1) 2 cb0 y0 cb0 y0+y1 2 cr-1+cr1 2 cr1 y1 cr1 y1+y2 2 cb0+cb2 2 cb2 y2 cb2 y2+y3 2 cr1+cr3 2 cr3 y3 cr3 y (n+2) cb (n+2) y(n)+y(n+1) 2 cr(n+1)+cr(n-1) 2 cb(n) y(n+1) cb(n)+cb(n+2) 2 cr(n+1) y(n+1)+y(n+2) 2 cr(n+1) cb(n)+cb(n+2) 2 y(n+2) cr(n+3)+cr(n+1) 2 cb(n+2) y(n+2)+y(n+3) 2 cr(n+3)+cr(n+1) 2 cb(n+2) cb2+cb4 2 clk y, cr (output) r, g, b (input) figure 20. rgb to ycbcr timing, mode = 111 rgb (0) y(0), cb (0) chs rgb (1) rgb (8) rgb (9) rgb (10) rgb (11) rgb (12) rgb (13) y(2), cr (2) y(4), cb (4) clk r, g, b (output) y, cr (input) figure 21. ycbcr to rgb timing, mode = 111 rgb (0) y(0), cb (0) chs rgb (1) rgb (2) rgb (3) rgb (4) rgb (5) y(2), cr (2) y(8), cb (8) y(10), cr (10) y(12), cb (12)
ZR36011 preliminary 12 absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. storage temperature........................................ -65 c to +150 c supply voltage to ground ....................................-0.3v to +7.0v dc output voltage ........................................ -0.3v to v cc +0.3v dc input voltage ........................................... -0.3v to v cc +0.3v dc input current ..............................................-10ma to +10ma operating range temperature .................................................... 0 c t a +70 c supply voltage ...........................................4.75v v cc 5.25v dc characteristics symbol parameter min typ max units test conditions v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage 0.4 v i ol = 2ma v oh output high voltage 2.4 v i oh = -400 m a i cc power supply current 90 ma v cc = 5.0 v, c l = 20pf, t a = 25 c, 30 mhz i li input leakage current 10 m av in = v cc or v ss i oz output leakage current 10 m av out = v cc or v ss , output disabled device under test 1.5v 2.4v 0.45v output input during ac testing, inputs are driven at 0.4v and 2.4v levels. unless othrewise specified, switching times are measured from the 1.5v level of dclk to the 0.8v or 2.0v levels at the input/output. 2.0v 0.8v 0.8v 2.0v figure 22. ac testing input, output test point from output under test 50pf figure 23. normal ac test load
ZR36011 13 preliminary ac characteristics symbol parameter min max units test conditions t cp clock period 33 ns t cwh clock high width 10 ns t cwl clock low width 10 ns t ds input data setup time 7 ns t dh input data hold time 1 ns t dd output data delay time 4 18 ns c l = 50pf t od output disable time 3 ns t oe output enable time 13 ns t os oe setup time 5 ns t oh oe hold time 1 ns t sw chs pulse width t cp t si chs setup time 3 ns t sh chs hold time 0 ns t rw rst pulse width 2*t cp t rs rst setup time 5 ns t rh rst hold time 1 ns figure 24. input timing requirements and output switching characteristics clk t cwh chs input output oe rst t cwl t cp t si t si t sh t rw t rh t sw t rs t os t oh t od t oe t ds t dh t od
ZR36011 preliminary 14 package information figure 25. ZR36011 plastic quad flat pack 100-pin flat pack pin assignment pin no pin name type pin no pin name type pin no pin name type pin no pin name type pin no pin name type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vss n.c. cb0 n.c. n.c. cr7 cr6 cr5 cr4 vss cr3 cr2 cr1 cr0 n.c. vcc n.c. y7 y6 y5 p - b - - b b b b p b b b b - p - b b b 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 y4 vss y3 y2 y1 y0 n.c. n.c. n.c. n.c. syc1 syc0 mode2 mode1 mode0 vcc bypass chs vss clk b p b b b b - - - - b b i i i p i i p i 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vcc rst dir oe sign vss cmy ccir srgb0 srgb1 n.c. n.c. n.c. n.c. r0 r1 r2 r3 r4 vss p i i i i p i i b b - - - - b b b b b p 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 r5 r6 r7 n.c. n.c. g0 vcc g1 g2 g3 g4 vss g5 g6 g7 n.c. n.c. b0 n.c. n.c. b b b - - b p b b b b p b b b - - b - - 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 b1 b2 b3 b4 vss b5 b6 b7 n.c. vss vcc n.c. cb7 cb6 cb5 vss cb4 cb3 cb2 cb1 b b b b p b b b - p p - b b b p b b b b p = power, i = input, b = bidirectional .012 .004 (.30 .10) .0256 typ (.65 .15) note: principal dimensions in inches, dimensions in brackets in millimeters. .551 .008 (14.00 .20) .007 +.0015/?003 (.18 +.04/?08) .031 .008 (.80 .20) seating plane .705 .015 (17.90 .40) .118 .014 (3.00 .35) .015 +.005/?015 (.38 +.13/?38) top view .782 .010 (20.00 .20) .941 .015 (23.90 .40) ZR36011 top view 1 30 31 50 51 80 81 100 vss n.c. cb0 n.c. n.c. cr7 cr6 cr5 cr4 vss cr3 cr2 cr1 cr0 n.c. vcc n.c. y7 y6 y5 y4 vss y3 y2 y1 y0 n.c. n.c. n.c. n.c. n.c. n.c. b0 n.c. n.c. g7 g6 g5 vss g4 g3 g2 g1 vcc g0 n.c. n.c. r7 r6 r5 vss r4 r3 r2 r1 r0 n.c. n.c. n.c. n.c. cb1 cb2 cb3 cb4 vss cb5 cb6 cb7 n.c. vcc vss n.c. b7 b6 b5 vss b4 b3 b2 b1 syc1 syc0 mode2 mode1 mode0 vdd bypass chs vss clk vcc rst dir oe sign vss cmy ccir srgb0 srgb1 pin 1 index mark, notched corner, or both. .006 (.15)
ZR36011 15 preliminary notes:
ds36011-0993 the material in this data sheet is for information only. zoran corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product speci?cations, operating characteristics, packaging, etc. zoran corporation assumes no liability for damage resulting from the use of information contained in this document. ZR36011 preliminary zr 36011 pq c ordering information screening key package part number prefix package screening key c - 0 c to +70 c (v cc = 4.75v to 5.25v) pq - plastic quad flat pack (eiaj) sales offices u.s. headquarters n zoran corporation 1705 wyatt drive santa clara, ca 95054 usa telephone: 408-986-1314 fax: 408-986-1240 japan operations n zoran corporation 1-5-3 ebisu kogetsu bldg. 4th floor shibuya-ku, tokyo japan telephone: 81-3-3448-1980 fax: 81-3-3448-1690 israel design center n zoran microelectronics, ltd. advanced technology center p.o. box 2495 haifa, 31024 israel telephone: 972-4-551-551 fax: 972-4-551-550

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